Flip-Flop Circuits: How Digital Memory Works

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SR: S=0 R=0 → Hold — Q retains its previous value

With both inputs low, the SR flip-flop holds its current state. This memory property — retaining state without continuous input — is what makes flip-flops the fundamental building block of registers and RAM.

Formula

SR: Q(next) = S + R'·Q, constraint S·R = 0
JK: Q(next) = J·Q' + K'·Q
D: Q(next) = D
T: Q(next) = T ⊕ Q

Memory from Logic

A flip-flop is the smallest possible memory — a circuit that stores exactly one bit. Unlike combinational logic where outputs depend only on current inputs, a flip-flop's output depends on its history. This feedback loop, where two cross-coupled gates reinforce each other, creates two stable states that persist until explicitly changed. Every register in your CPU, every bit of SRAM cache, uses flip-flops.

SR: Set and Reset

The SR (Set-Reset) flip-flop is the simplest type. Setting S=1, R=0 forces Q to 1. Setting S=0, R=1 forces Q to 0. With both inputs low, Q holds its previous value — this is the memory property. The forbidden state S=R=1 makes both outputs equal, breaking the expected Q̄=NOT(Q) relationship. This limitation led to the development of the JK flip-flop.

JK: The Universal Flip-Flop

The JK flip-flop resolves the SR forbidden state elegantly: when J=K=1, instead of producing undefined output, it toggles Q to its complement. Combined with the set, reset, and hold behaviors inherited from the SR design, the JK flip-flop is functionally complete for sequential logic. D and T flip-flops are simplified versions — D captures input directly, T toggles on command.

Clock Synchronization

Real flip-flops are edge-triggered: they only sample inputs at the rising or falling edge of a clock signal. Between clock edges, inputs can change freely without affecting the stored state. This synchronization ensures that all flip-flops in a circuit update simultaneously, preventing race conditions and enabling predictable sequential behavior at gigahertz speeds.

FAQ

What is a flip-flop in digital electronics?

A flip-flop is a bistable circuit that stores one bit of information. It has two stable states (Q=0 and Q=1) and changes state only in response to input signals, typically synchronized to a clock edge. Flip-flops are the fundamental building blocks of registers, counters, and all sequential logic.

What is the forbidden state in an SR flip-flop?

When both Set and Reset inputs are 1 simultaneously in an SR flip-flop, the outputs Q and Q̄ are both forced to 0 (in NOR-based) or both to 1 (in NAND-based), violating the requirement that Q̄ = NOT Q. This is the forbidden or invalid state. JK flip-flops solve this problem by toggling instead.

How does a JK flip-flop improve on an SR flip-flop?

The JK flip-flop behaves identically to the SR flip-flop when J and K differ, and holds state when both are 0. The key improvement is when J=K=1: instead of entering a forbidden state, the JK flip-flop toggles — Q changes to its complement. This makes the JK flip-flop fully defined for all inputs.

What is edge-triggered clocking?

Edge-triggered flip-flops sample their inputs only at the rising (or falling) edge of the clock signal, ignoring input changes at all other times. This prevents timing hazards and ensures predictable operation in synchronous digital systems. Most modern flip-flops are positive-edge-triggered.

Sources

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